量子机器学习框架统一建模器件
A Unified Physics-Aware Quantum Machine Learning Framework across Power GaN HEMTs and Logic Nanowire FETs: Predicting Unseen Process Splits and Held-Out Geometry Combinations with Lower Error and Tighter Split-to-Split Variability
清华团队用强化学习发现量子电路，在器件建模上误差降低59-84%，比6个经典方法都好。
研究人员提出统一强化学习框架，发现紧凑参数化量子电路用于数据稀缺器件建模。该框架在11个目标上实现最低平均绝对误差，比6个经典基线低59%误差(HEMTs的Ioff)和81%更紧的折叠变异性。对于NWFETs，误差降低84%(VTH, SS, Ioff)，折叠变异性紧缩82%。框架无需明确物理约束或特定方程，展现低OOD误差和改进物理一致性。
A Unified Physics-Aware Quantum Machine Learning Framework across Power GaN HEMTs and Logic Nanowire FETs: Predicting Unseen Process Splits and Held-Out Geometry Combinations with Lower Error and Tighter Split-to-Split Variability
We present a unified reinforcement-learning (RL) framework that discovers compact parametrized quantum circuits (PQCs) for data-scarce device modeling. A graph neural network (GNN) policy optimized by proximal policy optimization (PPO) searches circuit architectures using leave-one-group-out cross-validation (LOGOCV) error on held-out process or geometry groups as the reward. The framework achieves the lowest mean absolute error (MAE) on all 11 targets versus six classical baselines, with 59% lower error (Ioff) and 81% tighter fold variability (VTH) for HEMTs and 84% lower error (VTH, SS, Ioff) and 82% tighter fold variability (Ioff) for NWFETs. These results demonstrate the potential of RL-selected, classically simulated PQCs as compact surrogates with low OOD error and improved physical consistency, despite imposing no explicit physical constraints, penalty terms, or device-specific equations, on the two evaluated device datasets.