SLIC：用强化微调 4B 小模型做多轮模拟电路优化
SLIC: Reinforcement Fine-Tuning Small LMs for Multi-Turn Analog Circuit Optimization
模拟电路调参不再需要云端大模型：4B 小模型本地跑仿真闭环，Pass@1 反超 DeepSeek 的 763B 模型近 49 个百分点，还能跨工艺节点迁移。做 EDA 工具或芯片设计的工程师值得把它加进工具链，论文附带 41 个拓扑的开源基准可直接复现。
论文提出 SLIC（Small LM Iterating on Circuits），一个强化微调框架，训练 4B 级、可本地部署的语言模型做闭环模拟电路优化。仅用开源 65 nm CMOS 预测技术模型（PTM）训练，SLIC-Random 在分布内四规格 Pass@1 达 87.1%（八轮内完成），超过 763B 的 DeepSeek-V4.1-Flash Think 48.5 个百分点。
技术上，SLIC 把结构化电路表示与离散化相对更新动作配对，采用领域约束的多目标奖励，并引入 Reward-Guided Rollout Steering（RGRS），将每步仿真器反馈同时用于策略学习和在线 rollout 构建，应对稀疏奖励与强约束场景。作者还发布了含 41 个放大器拓扑的开源基准，覆盖分布内验证、held-out 拓扑评估和跨工艺节点迁移。
泛化方面，SLIC-Softmax 在 held-out 拓扑上达 72.6% Pass@1，策略无需再微调即可迁移到五个未见工艺节点，并在商用 TSMC 65 nm CMOS PDK 上取得 49.9% 的 held-out 拓扑 Pass@1；将测试时仿真交互轮数提升到 32 轮后，Pass@1 可达 83.2%。由于模型本地运行，专有 PDK 数据无需传输给外部 LLM 服务。
SLIC: Reinforcement Fine-Tuning Small LMs for Multi-Turn Analog Circuit Optimization
Analog integrated circuit (IC) design is a multi-turn, simulator-grounded engineering task that demands iterative reasoning over coupled performance tradeoffs, yet proprietary process design kits (PDKs) make hosted large language model workflows difficult to deploy in practical design settings. We present SLIC (Small LM Iterating on Circuits), a reinforcement fine-tuning framework that trains a 4B-scale, locally deployable language model for closed-loop analog circuit optimization. SLIC pairs structured circuit representations with discretized relative-update actions, domain- and success-gated multiobjective rewards, and Reward-Guided Rollout Steering (RGRS), which turns per-step simulator feedback into signals for both policy learning and online rollout construction in this sparse, highly constrained domain. We further release an open, goal-conditioned benchmark of 41 amplifier topologies with standardized protocols for in-distribution validation, held-out topology evaluation, and cross-technology-node transfer. Trained solely with open source 65 nm CMOS predictive technology models (PTM), SLIC-Random achieves 87.1% in-distribution four-specification Pass@1 within eight turns, surpassing the 763B DeepSeek-V4.1-Flash Think by 48.5 percentage points. Beyond the training distribution, SLIC-Softmax reaches 72.6% Pass@1 on held-out topologies, and the trained policies consistently transfer across five unseen technology nodes without additional fine-tuning. This transfer extends to a commercial TSMC 65 nm CMOS PDK, where SLIC-Random achieves 49.9% held-out-topology Pass@1, demonstrating practical deployment through local inference without transmitting proprietary data to external LLM services. Performance further scales with test-time simulator interactions, reaching up to 83.2% held-out-topology Pass@1 at a 32-turn budget.
本条情报归属 AITOP「论文」核心栏目，重点聚焦北美前沿实验室与硅谷科技巨头。在跨区域产业观察坐标中，该动态直接关联「AI 开发者工具链、Coding Agent 与工程化实践」研究主线，反映出当前技术演进与商业落地的最新风向。涉及核心实体与技术议题包括：SLIC、强化微调、模拟电路设计、TSMC，读者可通过下方标签进入对应专题页查阅历史脉络与关联对比。
信源核验说明：本文原始线索采编自「arXiv cs.LG」（@Yan Xu, Zhengqi Gao, Ching-Yun Ko, Zhang-Wei Hong, Wenjie Lu, Tao Yu, Xin Zhang, Duane S. Boning, Ruonan Han），经 AITOP 多维评分管线结构化提炼。