arXiv 论文提出 Vitis HLS 到 AWS FPGA 的完整工具链
Enabling AWS Cloud FPGA Development Using High-Level Vitis HLS
教 AI 编程助手直接写 FPGA 设计的论文，还公开了时序收敛和部署细节，做硬件加速的可以看看。
论文面向 AWS EC2 F2 云 FPGA 基础设施，实现了从 Vitis HLS 到 HDK 再到 AFI 的完整开发工作流，填补了 AWS FPGA 发布八年来学术文献中的空白。作者提出 FP32 PyTorch、比特精确量化 Python、HLS C-simulation、物理 FPGA 四层方法论，用于定位包括 FPGA 电路错误在内的各类问题。验证环节使用针对命名实体识别微调的 TinyBERT，在 FPGA 上部署了嵌入层和四层编码器中的第一层。权重从主机 DRAM 流式读取导致性能不及 CPU/GPU 实现，论文讨论了后续改进路径。
Enabling AWS Cloud FPGA Development Using High-Level Vitis HLS
We present a toolchain for development of ML models on AWS EC2 F2 cloud FPGA infrastructure from high-level language, implementing a complete Vitis HLS to HDK bridge to AFI workflow that has been absent from the academic literature despite eight years of AWS FPGA availability. We introduce a four-level methodology (FP32 PyTorch, bit-accurate quantized Python, HLS C-simulation, physical FPGA) to aid in localizing errors, including FPGA-specific circuit errors. Together these tools allow coding agents to effectively implement FPGA designs from user directions, testing and debugging as needed. We document the deployment workflow, timing closure strategies, and practical HLS engineering decisions that proved crucial. We validate using TinyBERT fine-tuned for address Named Entity Recognition, implementing the embedding layer and the first of four encoder layers on the FPGA hardware. Our implementation streams weights from host DRAM, yielding poor performance compared to CPU/GPU implementations; we discuss forward paths.
